Scor­pio News

Interrupts

The Z280 processor has a compatible interrupt structure with the Z80 in modes 0, 1 and 2 both maskable and non-maskable interrupts are completely compatible with the Z80.

In addition to these original modes, Zilog have added a fourth, more advanced interrupt mode, IM3. This is upwards compatible with the Z80. This mode is similar to mode 2, except that instead of saving only the return address, also the “Master Status Register” and 16-Bit “Reason code” are saved. A new “Master States Register” and Program counter are fetched from the “Interrupt/​Trap vector table”. The “Reason code” is the vector address of the interrupting device. The contents of the “Master Status Register” decides, amongst other things, the interrupt levels that are enabled and whether the interrupt routine is user or System mode.

A further enhancement is that there are 3 (Maskable) interrupt lines to the CPU. This is a binary coding of 7 different interrupt levels. Each level can be separately enabled or disabled (by 7 bits in the MSR). This means that certain interrupt devices can optionally interrupt lower-level interrupt routines. This provides a nested interrupt structure, nice.

There is a separate stack used to store the return address of interrupted code. This keeps the user stack free for use within the program. No problem any more with user stack space, its just not used at all.

I remember the old Nascom monitor (Nas-Sys 1) had a problem, where data was left vulnerably (bad programming) on the stack. Any interrupt overwrote this data producing a bombed-out system. This would not happen to the Z280. Perhaps Nascom should have used the Z280 for the Nascom (you can interrupt me if you like, but don’t expect me still to be there when you return) 2 monitor.

Also, unlike the Z80, Block moves, Block compare and Block I/O can all be interrupted before the end of the block.

TRAPS

Traps are Software interrupts, similar to the external interrupts, except that they originate from the codes or condition code. Eight trap are implemented for Single-step, Breakpoint-on-halt, Divide by zero, Stack overflow, memory transgression, system call and privileged instructions.

64K OF I/O PORTS

Paged blocks of I/O addresses, giving 256x256 or 64K ports. That’s probably enough for most of us. Again, cleverly completely compatible with existing Z80 code.

Access to more than the usual 256 ports is (yes..​you guessed it) via the processor “I/O Page register”. Pity that 80-BUS boards only decode the bottom 8 bits. What about decoding whole racks though !!!

AND THE REST…

In this short (?) overview of this board, the Editor would not let me mention in detail the 3 16-bit counter/​timers, Full duplex UART, 10 bit DRAM refresh, Multi CPU design, 4 DMA channels, Auto program bootstrap via UART, Dual Stack pointers (User & system), Single Step operation, etc.

Conclusion

I have found the board to be an excellent addition to my system, akin to putting a Concorde afterburner on my ageing MG.

Gemini tell me that the new version will probably have multi-processing capabilities, allowing up to 4 GM890s on the same bus..

I have just read that a Z280 assembler is available. Named the XZ280, it supports all Z80 instructions, together with all additional Z280 instructions. The assembler is from Real Time Systems, in the Isle Of Man. Phone ____-_____.