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To disable a CTC channel from causing an interrupt, the code is simple. Just write a 01H to the appropriate channel. Like the other Z80 chips, it is necessary to disable the system interrupts in case an interrupt occurs while the disable instruction is being assimilated by the I/O chip. The code is only slightly more complex than above:

LD   A, 01h
DI             ; Disable CPU interrupts
OUT (CTCn),A   ; Disable CTC channel
EI             ; re-enable CPU interrupts

A channel may not begin operations in any mode unless a valid time constant byte has been written into the Time Constant Register. This byte is expected on the next write to the channel in question following the write of the channel control byte, provided the channel control byte had bit 2 set (= 1). If this time constant byte is 0 it is interpreted as 256. If a new time constant byte written to a channel already in operation, the new time constant byte is only reloaded at the next count down to zero.

The major difference between Counter mode and Timer mode is that Counter mode uses the external clock or pulse provided on the CLK/​TRGn pin, whereas the Timer mode uses the system clock, divided by the prescaler (either 16 or 256 according to the setting of bit 5 of the channel control byte). In timer mode, the timing operation can be programmed to start from an external trigger to the CLK/​TRGn pulse, or almost immediately from the system signals. The external starting trigger is usually not required, and the reader is referred to the manufacturer’s data sheets for more precise details. It is also possible to define whether the trigger or count decrement takes place on the rising or falling edge of the timing clock (Bit 4). One constraint that is not very openly defined is to be found in the technical details of the data sheet; this states that the maximum frequency to be applied to the CLK/​TRGn pin is to be half of the system clock. This means that on a 4MHz system, the maximum external clock to the CHC is to be 2 MHz.

Now for a worked example. In the case of a standard MAP CPU, we wish to set up the CTC as follows:

Rather than give a full listing of code, I will use the method set out in [5] for I/O port initialization, with comments beside the relevant bytes to explain how they are arrived at. These initialization tables are set out like this: