| PIN | | SIGNAL | DESCRIPTION |
|---|
| 1 | | GND | Ground |
| 2 | | GND | Ground |
| 3 | | GND | Ground |
| 4 | | GND | Ground |
| 5 | | CLOCK | System clock |
| 6 | * | /NMI SW | A low on this line initiates a short pulse on line 21 |
| 7 | | RSFU | Reserved for future use |
| 8 | | AUX CLK | 4MHz clock signal (optional) |
| 9 | * | /RAM DIS | Ram disable |
| 10 | * | /RESET SW | Reset switch |
| 11 | * | /NAS MEM | Memory decode to Nascom 1 |
| 12 | * | /NAS IO | I/O decode to Nascom 1 and 2 |
| 13 | * | /DBDR | Data bus drive, used to change the direction of the data bus buffers on the buffer board or Supermum. |
| 14 | * | /RESET | 50uS reset pulse, resets entire system. |
| 15 | | /HALT | Z80 halt signal |
| 16 | | /BAL | DMA |
| 17 | | /BAO | daisy chain |
| 18 | | /BUSRQ | Z80 bus request |
| 19 | | IEI | Interrupt |
| 20 | | IEO | daisy chain |
| 21 | * | /NMI | Z80 NMI line, (not used by N1) |
| 22 | * | /INT | Z80 interrupt line |
| 23 | * | /WAIT | Z80 wait line |
| 24 | | /RFSH | Z80 refresh signal |
| 25 | | /M1 | Z80 opcode fetch signal |
| 26 | | /TORQ | Z80 input/output signal |
| 27 | | /MREQ | Z80 memory signal |
| 28 | | /WR | Z80 write signal |
| 29 | | /RD | Z80 read signal |
| 30 | | A0 | |
| 31 | | A1 | |
| 32 | | A2 | |
| 33 | | A3 | |
| 34 | | A4 | |
| 35 | | AS | |
| 36 | | A6 | |
| 37 | | A7 | |
| 38 | | A8 | Z80 16 bit |
| 39 | | A9 | address bus |
| 40 | | A10 | |
| 41 | | A11 | |
| 42 | | A12 | |
| 43 | | A13 | |
| 44 | | A14 | |
| 45 | | A15 | |
| 46 | | A16 | Optional implementation |
| 47 | | A17 | for extended |
| 48 | | A18 | addressing. |
| 49 | | GND | Ground to seperate the data and address busses. |
| 50 | | D0 | |
| 51 | | D1 | |
| 52 | | D2 | |
| 53 | | D3 | Bidirectional data bus. |
| 54 | | D4 | |
| 55 | | D5 | |
| 56 | | D6 | |
| 57 | | D7 | |